Flip flops are different than combinatorial logic (such as AND and OR gates) in that a flip flop’s output (Q) changes in response to a clock input and its output state is governed by the logic levels present on its other inputs.

    The following table characterizes how the flip flop behaves based on its inputs. For each flip flop type (SR for set/rest, JK, D for delay, and T for toggle) there are two tables shown. The first is the Characteristics Table and the Excitation Table. The flip flop itself only works in one way and the two tables provide different ways to view its behavior.

    In the Characteristics Table, the control inputs (for example S & R) are shown first and the output after the next clock input (Q next) is shown next in the table. In the Excitation Table, the current Q output (Q) is shown first and the the Q output after the next clock (Q next) is shown second based on the state of the other inputs (S & R or J & K for example).

    The clock input to a flip flop can be based on its level (a valid logic 1 or 0) or its edge (moving from 0 to 1 or 1 to 0). Consult the data sheet for the specific part of interest to determine what constitutes a valid clock input.