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Logic Gate Oscillator

Schematic for a logic gate oscillator.

    CMOS gates (ones with a switching threshold around 50% of Vcc with a relatively low input current) can be configured to oscillate with the addition of resistors and a capacitor. The configuration shown here is guaranteed to oscillate, operates over a wide frequency range, and will have a duty cycle near 50%.

    Entering a value for the frequency (f), will find R and C. You can optionally enter a value for R or C along with f to find the missing value. Entering values for both R and C will find f. A default value of 5% is assumed for the capacitor’s tolerance. If you wish to use another value, enter it as a percentage (10% = 10).

    The oscillator shown uses three inverters. Any combination of inverting gates can be used. This is useful if there are spare gates available in other packages.

    For a sine wave oscillator, use the Sine and Cosine solver. The following formulas are used in this solver.

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